It’s Time
for Retym
Our global team is growing!
Our team is growing quickly, with our headquarters in Silicon Valley, California and our design center in Tel Aviv, Israel.
We’re looking for candidates who thrive in a startup environment to make big contributions to a technology positioned to make a difference in data center infrastructure.
The Retym team is a passionate and cohesive group that is always collaborating as we work towards our mission. If you’re interested in joining us, please apply below.
Senior Verification Engineer
About The Position
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.
Requirements
Requirements
- 6+ years of experience – a must
- Performed at last 2 or more full block/system verification cycles.
- In depth knowledge in VLSI verification flow, languages and concepts.
- Experience in data path or data protocols, specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM, UVM, OVM).
Responsibilities
- Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
- Build verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for corner-cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrices to close the full functionality.
Apply for this position
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